In U.S. Pat. No. 6,413,822, for the purpose of providing over-voltage ESD protection, a Zener diode is formed at the peripheral area or gate pad area of the MOSFET device. The Zener diode is supported on a thick oxide layer and includes an array of doped regions arranged as n+pn+pn+ regions. However, the prior art still has technical difficulties in dealing with the ESD problems in manufacturing. Specifically, damage of the gate oxide layer and the Si area of the body region can easily be induced during the dry oxide etch to etch the thick oxide layer prior to source ion implantation because there is no a stopper layer to protect the body region and the channel region during the dry oxide etch process, therefore the device may suffer over-etch in gate oxide and channel region, as shown in FIG. 1. On the other hand, it also may cause Si damage when there is no screen oxide for the subsequent source ion implantation in the process. Even if the screen oxide for source ion implantation is grown, Boron near channel region will leach out during screen oxidation, which will cause punch-through issue.
Therefore, there is still a need in the art of the semiconductor device fabrication, particularly for trenched power semiconductor design and fabrication, to provide a novel cell structure, device configuration and fabrication process that would resolve these difficulties and design limitations. Specifically, it is desirable to provide effective method to reduce a likelihood of device damages caused in fabrication process. In the meantime, it is also desirable to eliminate the problem caused by punch-through issue.